A trace-driven profiler for RISC-V that analyses execution traces to recommend which ISA extensions and custom sub-instructions are actually worth putting in hardware. It reports cycle counts and instruction mix per extension across the Embench suite, so a speed-up can be weighed against the area and power an extension would cost. Presented as a poster at OSCAR (ISCA'24) and at HiPCW 2025.

A ParaGato Labs project on architecture- and memory-centric design space exploration for DNN-based genomic basecalling on heterogeneous RISC-V systems at the edge. Nanopore basecallers normally lean on GPUs to keep pace with sequencing rates; Ginger-V asks when an FPGA-backed RISC-V platform can sustain them instead, under real power and memory budgets. GEMM-dominant kernels are offloaded to RedMulE, the PULP platform's outer-product systolic GEMM accelerator, while control, activations and decoding stay on the RISC-V host with selective custom instructions. The study centres on memory traffic and data movement, tiling and reuse, arithmetic intensity, and real-time feasibility against nanopore signal rates.

A resource-constrained FPGA accelerator for sparse-dense matrix multiplication, implemented for 560x560 matrices. It explores the dataflow and memory-access strategies that keep utilisation high when one operand is sparse and the other dense, so high-throughput AI/ML kernels still fit on modest FPGA fabric. Received the Best Paper Award at VLSID 2022.

Course material I built and taught for undergraduate electronics students at the CHIPS Lab, PES University. It ships Vivado project files for the Pinaka SoC - a 32-bit Shakti RISC-V core targeting Arty A7-35 and A7-100 boards - alongside labs that take students from running C on the Spike simulator and measuring cycle counts, through programming the board, to designing and packaging their own custom AXI4 peripheral and running code against it.