Ashuthosh

I am a hardware researcher and systems engineer working at the intersection of computer architecture, performance modeling, and hardware–software co-design.

My work focuses on building efficient compute systems through architectural insight and rigorous performance analysis. I have developed analytical models, profiling frameworks, and custom compute kernels for RISC-V and FPGA-based platforms, with a focus on accelerating sparse and dense linear algebra as well as graph workloads.

I am particularly interested in microarchitectural bottleneck analysis, memory hierarchy behavior, and compute–memory trade-offs in many-core systems. I genuinely enjoy working hands-on with FPGAs — using them as experimental platforms to prototype architectural ideas, validate performance models, and explore design-space trade-offs before silicon.

Currently, I serve as a Senior Design Engineer at Calligo Technologies, contributing to advanced hardware system design. I am also actively involved with CHIPS Lab, PES University, where I mentor students and pursue independent open-source research in computer architecture.

Beyond performance metrics and benchmarks, I am motivated by a broader mission: building computing systems that are efficient, responsible, and purposeful. I believe architecture should enable meaningful scientific and engineering progress — from large-scale computation to sustainable infrastructure and space-grade systems — not merely short-term trends.

Outside engineering, I explore photography as a way of observing structure, light, and perspective from a different lens.